[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Astera Labs jobs](https://jobs.opennash.com/companies/astera-labs/) · [Search jobs](/search/) Astera Labs · Taiwan # Principal Digital Design Engineer Taiwan Senior individual contributor Design Listed on Astera Labs’s official careers site. Posted September 14, 2026. Check that it is still open and apply there. [Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4733735005) [OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Digital Design Engineer ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. ### Overview Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. ### Key Responsibilities Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design. Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues. Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. Work closely with post-silicon teams to facilitate silicon bring-up and debug. Mentor junior engineers to develop their technical skills and expertise. Actively contribute to the development and improvement of silicon development processes. Drive designs to production, ensuring accountability for quality, schedule, and overall design success. ### Required Qualifications Education & Experience: Bachelor’s degree in electrical engineering or equivalent. 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets Digital Design Expertise: Architecture definition and micro-architecture development RTL coding, functional simulation, and synthesis Timing closure and gate-level simulation (GLS) Design for test (DFT) implementation Production experience with advanced CMOS nodes (≤7nm) ### Protocols & Integration Deep expertise in at least one high-speed protocol—PCIe, Ethernet, InfiniBand, DDR, or similar Third-party IP integration and verification. Block-level design ownership from architecture through GDS Tools & Methodologies: Proficiency with Cadence and/or Synopsys digital design flows Familiarity with UVM-based verification methodologies. Silicon bring-up, debug, and failure analysis expertise Professional Attributes: Strong work ethic with the ability to balance multiple priorities in a dynamic environment Excellent communication and collaboration skills; comfortable working cross-functionally with global teams Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements Customer-focused mindset with ability to translate business needs into technical excellence ### Preferred Qualifications - Track record of delivering multiple high-performance designs to production in data-center environments Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints - Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.) - Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality The base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## At a glance - Posted by the employer: Sep 14, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 34 days - Location: Taiwan[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4733735005) ## More jobs at Astera Labs ### [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://jobs.opennash.com/companies/astera-labs/jobs/b3492c70100b774b30cb/) Taiwan ### [Principal/ Sr Principal Digital Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/55bf35544b196196cda9/) Taiwan ### [AE| Principal Product Application Engineer (Scorpio)](https://jobs.opennash.com/companies/astera-labs/jobs/f0300d1ac0edbe7381b1/) Taiwan ### [Principal Advanced Packaging Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/39ff922c5f18ef6e9b56/) Taiwan ### [Analog Mixed Signal Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/b79c33909c027beb9e25/) Singapore ## Similar jobs at other companies ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Senior / Staff Engineer - Digital Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/6af7082b2823e36216a0/) Infineon Technologies · Singapore ### [Digital Design Verification Engineer, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/a645ad2a0d00db966bb8/) Qualcomm · Toronto, Ontario, Canada ### [Digital Design R&D Engineer (Lead/Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/0573bd8ee5eabfcd66a7/) Qualcomm · Bangalore, India ### [Lead Engineer - Digital Design](https://jobs.opennash.com/companies/eaton/jobs/6e5c212cf2b7e641eb70/) Eaton · Hadapsar, Pune, Maharashtra, IND OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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