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Astera Labs · Bengaluru

# Principal Logic Design Engineer - UALink IP/Subsystem

Bengaluru Senior individual contributor Design 

Listed on Astera Labs’s official careers site. Posted September 17, 2026. Check that it is still open and apply there.
[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735009005)

[OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Logic Design Engineer - UALink IP/Subsystem

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Principal Logic Design Engineer – UALink IP/Subsystem Experience 10–15 years

### Job Summary

We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.

### Key Responsibilities

Lead architecture and RTL development for UALink IP/subsystems. Translate protocol and system requirements into scalable hardware architecture. Design high-bandwidth, low-latency data paths and control logic. Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability. Define interfaces between UALink and other SoC/interconnect components. Develop and review SystemVerilog RTL.

Drive design optimization for performance, power, area, and latency. Work closely with verification, physical design, SoC integration, and firmware teams. Review design specifications and contribute to architectural decisions. Debug complex simulation and integration issues. Provide technical leadership and mentorship.

### Required Skills

Strong experience in RTL and microarchitecture development. Experience with high-speed interconnects and/or coherent fabrics. Strong understanding of computer architecture, networking/interconnect concepts, and data movement. Proficiency in SystemVerilog/Verilog. Strong understanding of CDC, reset architecture, performance, and hardware design methodology. Preferred Direct UALink experience. Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.

Experience in AI/accelerator or high-performance compute systems. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## At a glance
- Posted by the employer: Sep 17, 2026
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 31 days
- Location: Bengaluru[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735009005)

## More jobs at Astera Labs

### [IP Design Director](https://jobs.opennash.com/companies/astera-labs/jobs/9f1c471890ffa9586d40/)

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### [IP Design Verification Director](https://jobs.opennash.com/companies/astera-labs/jobs/c7d77a7b42b44dc5d852/)

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### [Lead Logic Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/6dd333afd34ce9ded283/)

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### [Principal Design Verification Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/5336f36070d4eca97510/)

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