[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Astera Labs jobs](https://jobs.opennash.com/companies/astera-labs/) · [Search jobs](/search/) Astera Labs · San Jose # Senior Packaging Integration Lead San Jose Manager or lead Operations Listed on Astera Labs’s official careers site. Posted September 22, 2026. Check that it is still open and apply there. [Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735854005) [OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Senior Packaging Integration Lead ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. ### Job Description We are seeking a Senior Packaging Integration Lead to serve as the single-threaded packaging owner for one or more of Astera Labs’ advanced connectivity products. This role owns the end-to-end packaging solution from customer requirements and package architecture definition through development, qualification, and production ramp & represents packaging across the customer, internal cross-functional teams, business units, and the OSAT, foundry, and substrate supply base. This is a senior individual-contributor technical leadership role who can set packaging technical direction, make architecture and technology-selection decisions, and drive alignment across stakeholders without direct authority. You will partner with packaging leadership on strategy while owning the technical direction for your products — defining package architecture and test vehicles to de-risk technology, and guiding execution engineers and external partners to deliver robust, manufacturable packages on schedule. ### Key Responsibilities - Own the packaging solution end-to-end for assigned products — serve as the single point of accountability from a packaging standpoint across definition, development, qualification, and production ramp - Act as the primary packaging interface to the customer: capture and translate customer packaging, mechanical, thermal, SIPI, and reliability requirements into package architecture, specifications, and a clear execution roadmap - Define package architecture, structure and technology selection (e.g., 2.5D/3D integration, chiplet/interposer, CoWoS-class, organic substrate) with feasibility, cost, performance, and manufacturability trade-off analysis - Define and drive test vehicle (TV) strategy and requirements to de-risk new package technology, characterize interconnect/SIPI performance, and validate assembly and reliability ahead of product builds - Represent packaging across internal cross-functional teams — silicon design, package design, SIPI, thermal, product engineering, test engineering, validation, quality, and operations — and align packaging requirements to product and business-unit roadmaps - Partner with product planning, architecture, and program management on product roadmap, packaging feasibility, technology readiness, cost targets, and schedule commitments - Set technical direction with OSAT, foundry & substrate partners — driving technology selection, design-rule alignment, and development roadmaps across the supply base - Own package definition deliverables and sign-offs, including POR/TOR, design rules, stack-up, package BOM, DFM alignment, and pre-tape-out design-integration readiness - Drive risk identification, technology-gap closure, and mitigation across the product’s packaging roadmap; escalate and resolve critical cross-functional and supplier issues with urgency. Communicate packaging status, risks, and key decisions to executive leadership, customers, and cross-functional stakeholders & external partners. ### Basic Qualifications B.S. or M.S. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related discipline; advanced degree preferred. 5-7+ yrs of experience in advanced packaging technologies such as 2.5D/3D integration, TSV, chiplets, and interposers. Optical / co-packaged optics experience is a plus. Demonstrated end-to-end ownership of a product or platform packaging solution, from definition and architecture through qualification and production ramp Experience defining package architecture and driving technology selection, including trade-off analysis across performance, cost, reliability, and manufacturability Experience defining test vehicles and characterization/qualification strategies to de-risk new packaging technology. Direct customer-facing experience translating product and system requirements into package specifications and commitments. Strong architecture-level understanding of signal/power integrity (SIPI), thermal, and thermo-mechanical reliability considerations in advanced packages Proven ability to lead and influence across internal cross-functional teams, business units, and external OSAT/foundry/substrate partners without direct authority. Hands-on background working with foundries, OSATs, substrate suppliers, and material vendors. Excellent communication, organizational, and executive-level presentation skills, with the ability to drive alignment across globally distributed teams. ### Preferred Qualifications Experience with UCIe / die-to-die interconnect and high-bandwidth chiplet integration Experience with CoWoS-class, silicon-bridge, or advanced fan-out packaging platforms Experience with co-packaged optics / optical packaging for scale-up connectivity Track record engaging foundry and OSAT partners on advanced-packaging technology roadmaps We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## At a glance - Posted by the employer: Sep 22, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 26 days - Location: San Jose[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735854005) ## More jobs at Astera Labs ### [(Sr.) Principal Engineer - Field Applications](https://jobs.opennash.com/companies/astera-labs/jobs/b3d9698444b34bdad944/) San Jose ### [Active Electric Cable / Smart Cable Module Lead, AVP](https://jobs.opennash.com/companies/astera-labs/jobs/5729079b36b918beca94/) San Jose ### [Applications Engineering Manager - Ethernet](https://jobs.opennash.com/companies/astera-labs/jobs/ec4146ac75f324fcad12/) San Jose ### [Distinguished Formal Verification](https://jobs.opennash.com/companies/astera-labs/jobs/8acc4f006011f2371073/) San Jose ### [Fabric Modeling and Analysis Engineer for Scale Up Fabric](https://jobs.opennash.com/companies/astera-labs/jobs/0443cc7ea898148d1e5f/) San Jose ## Similar jobs at other companies ### [Packaging Technology Integration, Senior Staff Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/dc3654c942cb55f78aaa/) Qualcomm · Singapore, Central Singapore ### [Process Engineer 5 (Advanced Packaging Integration Technologist)](https://jobs.opennash.com/companies/lam-research/jobs/23214597426c8f31b821/) Lam Research · Tualatin, OR, US ### [Advanced Packaging Principle Integration Technologist (Principal Engineer, 10 years+ experience)](https://jobs.opennash.com/companies/merck-kgaa-germany/jobs/6c7a051f85398fd2e61e/) Merck KGaA, Darmstadt, Germany and its affiliates · Hsinchu, Hsinchu County, Taiwan ### [Semiconductor Packaging Integration Research Manager](https://jobs.opennash.com/companies/intel/jobs/2e7798211332bf7b8b1a/) Intel ### [3D Integration & Advanced Packaging Expert](https://jobs.opennash.com/companies/asml-holding/jobs/7b44e023e68e46637bad/) ASML Holding · Hwasung, Korea OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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