[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Astera Labs · San Jose # Principal Post-Silicon Validation Engineer San Jose Senior individual contributor $207,000 to $230,000 Operations Listed on Astera Labs’s official careers site. Posted October 20, 2026. Check that it is still open and apply there. [Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4736479005) [OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Post-Silicon Validation Engineer ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. ### Role Overview Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues. As AI workloads scale into rack-level infrastructure, every link has to perform flawlessly. Your work will directly shape the quality, performance, and time-to-market of the products that connect the world's most advanced AI platforms, in a hyper-growth company where your technical judgment carries real weight. ### Key Responsibilities Post-Silicon Validation Leadership Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release - Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams - Lead lab bring-up of new silicon, including board, firmware, and software readiness Debug and Characterization Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary Characterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperature - Partner with design and DFT teams to feed findings back into current and future product generations ### Automation and Infrastructure - Develop scalable validation automation frameworks and test content using Python and C/C++ Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput - Analyze large validation datasets to identify trends, outliers, and risks early ### Technical Leadership - Mentor engineers and set best practices for validation methodology across the team Collaborate with customers and Field Applications Engineers to reproduce and resolve system-level issues ### Basic Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer - Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies - Strong scripting and programming skills in Python and/or C/C++ for test automation - Proven ability to debug complex hardware and firmware issues to root cause ### Preferred Qualifications - Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products Experience with SerDes characterization, equalization tuning, and link margining - Track record of taking multiple products from first silicon to volume production - Strong cross-functional communication skills and the ability to lead without direct authority Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## At a glance - Posted by the employer: Oct 20, 2026 - First seen by OpenNash: Oct 25, 2026 - Last checked: Nov 1, 2026 - Listed for: 12 days - Location: San Jose - Pay: $207,000 to $230,000[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4736479005) ## Hiring at Astera Labs - Open jobs: 170 - New in the last 7 days: After two weekly collections - Tracked since: Jul 12, 2026 [All Astera Labs jobs](https://jobs.opennash.com/companies/astera-labs/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Astera Labs ### [Active Electric Cable / Smart Cable Module Lead, AVP](https://jobs.opennash.com/companies/astera-labs/jobs/5729079b36b918beca94/) San Jose ### [Applications Engineering Manager - Ethernet](https://jobs.opennash.com/companies/astera-labs/jobs/ec4146ac75f324fcad12/) San Jose ### [Hardware Lab Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/eb4f36ec3a00782935f7/) San Jose ### [Performance Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/8b8a1db03a64a7bf79cf/) San Jose ### [Principal ATE Test Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/f4c49e519df3f435f9cc/) San Jose ## Similar jobs at other companies ### [Software Post Silicon Validation Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/13bd6141350cbf68c621/) Cisco Systems · Caesarea, Israel ### [Senior Lead Post-Silicon validation Engineer - SMMU](https://jobs.opennash.com/companies/qualcomm/jobs/7c702058744426b241b6/) Qualcomm · Bangalore, India ### [Pre/Post Silicon Validation Engineer with PMIC Expertise](https://jobs.opennash.com/companies/qualcomm/jobs/a8066ff98b0591b44533/) Qualcomm · Bangalore, India ### [Principal Post-Silicon System Validation Engineer](https://jobs.opennash.com/companies/on-semiconductor/jobs/0b11f17e3d835943c6d2/) ON Semiconductor · Bangalore, Karnataka, India ### [Principal Post-Silicon Validation Engineer](https://jobs.opennash.com/companies/on-semiconductor/jobs/bc9e60424c272c22a845/) ON Semiconductor · Bangalore, Karnataka, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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