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Astera Labs · Ho Chi Minh City

# Principal Analog Mixed-Signal Design Engineer

Ho Chi Minh City Senior individual contributor Design 

Listed on Astera Labs’s official careers site. Posted September 18, 2026. Check that it is still open and apply there.
[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735377005)

[OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Analog Mixed-Signal Design Engineer

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. About the Role We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the FinFET technology node.

In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes.

### Key Responsibilities

Design critical AMS blocks such as PLLs, CDRs, TX drivers, RX front-ends, CTLEs, DFE, LDOs, bias generators, and ADC/DAC components for wireline transceivers. Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners. Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design.

Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep). Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions. Create and maintain design documentation, design reviews, and specifications. Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior. Support silicon bring-up, lab measurement correlation, and debug of design issues.

Use industry-standard tools (e.g., Virtuoso, Spectre, ADE, MATLAB, Python) for design and analysis.

### Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field. 8+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.

Strong experience with: Transistor-level design and simulation in advanced nodes (≤ 5nm). Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends). SPICE simulation tools and AMS verification environments. Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs. Familiarity with layout interaction and parasitic-aware circuit optimization.

Solid debugging, problem-solving, and documentation skills.

### Benefits

Competitive salary. Performance bonus each year. Long-term Incentive (refreshed each year). Flexible working time. Health check each year. Insurance for engineer and family. Lunch Allowance. Company trips. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## At a glance
- Posted by the employer: Sep 18, 2026
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 30 days
- Location: Ho Chi Minh City[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4735377005)

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