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Astera Labs · San Jose

# Senior Digital Design Engineer

San Jose Senior individual contributor Design 

Listed on Astera Labs’s official careers site. Posted September 28, 2026. Check that it is still open and apply there.
[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4738468005)

[OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Senior Digital Design Engineer

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Discover more at www.asteralabs.com.

### Job Description

We are looking for Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration for high performance network controllers. The candidate is preferred to have knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

### Basic Qualifications

Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. Professional attitude with the ability to prioritize a dynamic list of multiple tasks. Entrepreneurial, open-mind behavior and can-do attitude. Authorized to work in the US and start immediately.

### Required Experience

Hands-on, prefer knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design skill – architecture, RTL, simulations and synthesis Experience with Synopsys and/or Cadence digital design tools/flows
- Knowledge of design for test (DFT)
- Familiarity with UVM based design verification Silicon bring-up and debug experience Preferred Experience: Scripting with Python or other equivalent programming languages.

Development/support for PCIe or Ethernet Switch products. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## At a glance
- Posted by the employer: Sep 28, 2026
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 20 days
- Location: San Jose[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4738468005)

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### [Principal Analog Mixed-Signal Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/1619cfdca7bbff7012a0/)

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