[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Astera Labs jobs](https://jobs.opennash.com/companies/astera-labs/) · [Search jobs](/search/) Astera Labs · San Jose # Principal Design Verification Engineer- SerDes/PHY IP San Jose Senior individual contributor $207,000 to $230,000 Design Listed on Astera Labs’s official careers site. Posted August 31, 2026. Check that it is still open and apply there. [Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4729354005) [OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Design Verification Engineer- SerDes/PHY IP ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. ### Role Overview Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. ### Key Responsibilities Verification Architecture & Strategy Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers - Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks - Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows Execution & Coverage Closure Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes - Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios - Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out Physical Layer & Protocol Verification Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards - Model and validate channel behavior, link training state machines, and analog handoff scenarios - Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks ### Cross-Functional Leadership - Mentor junior DV engineers and set technical direction across the verification team Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams - Contribute to verification IP reuse strategy and tooling improvements across product lines ### Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up Expert-level proficiency in SystemVerilog and UVM Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM) Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL ### Preferred Qualifications MS or PhD in Electrical Engineering or Computer Engineering Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows Scripting proficiency in Python or Perl for verification automation and regression management Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## At a glance - Posted by the employer: Aug 31, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 48 days - Location: San Jose - Pay: $207,000 to $230,000[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4729354005) ## More jobs at Astera Labs ### [Design Verification Tech Lead- SerDes/PHY IP](https://jobs.opennash.com/companies/astera-labs/jobs/1e85866cfa743b0673c9/) San Jose ### [Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms](https://jobs.opennash.com/companies/astera-labs/jobs/5b67cc84296369be4c16/) San Jose ### [Manager, Package Design Engineering](https://jobs.opennash.com/companies/astera-labs/jobs/3878ab9d89d33122f373/) San Jose ### [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://jobs.opennash.com/companies/astera-labs/jobs/6af1a1503a0f9512eca2/) San Jose ### [Principal Analog Mixed-Signal Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/1619cfdca7bbff7012a0/) San Jose ## Similar jobs at other companies ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [SoC Design Verification Engineer (Up to Principal Level)](https://jobs.opennash.com/companies/qualcomm/jobs/07fc1a63fb397059f4c8/) Qualcomm · Ho Chi Minh, Hồ Chí Minh, Vietnam ### [Design Verification Engineer](https://jobs.opennash.com/companies/siemens/jobs/3469736e66b7ab53255d/) Siemens ### [Design Verification Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/e0e64d6ed7ea9cff1d03/) Microsoft · India, Karnataka, Bangalore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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