[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Astera Labs jobs](https://jobs.opennash.com/companies/astera-labs/) · [Search jobs](/search/) Astera Labs · San Jose # Principal Digital Design Engineer San Jose Senior individual contributor Design Listed on Astera Labs’s official careers site. Posted September 14, 2026. Check that it is still open and apply there. [Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4732863005) [OpenNash Jobs](https://jobs.opennash.com/) / [Astera Labs](https://jobs.opennash.com/companies/astera-labs/) / Principal Digital Design Engineer ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. ### Job Description We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. ### Basic Qualifications Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. ### Required Experience Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc. Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc. Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production Experience with Synopsys and/or Cadence digital design tools/flows Good knowledge of design for test (DFT), stuck-at and transition scan test insertion Familiarity with UVM based design verification Silicon bring-up and debug expertise Small-geometry CMOS (≤28nm) design Preferred Experience: Firmware development with C-language, scripting with Python or other equivalent programming languages. Development/support for PCIe or Ethernet Switch products. The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## At a glance - Posted by the employer: Sep 14, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 34 days - Location: San Jose[Apply on Astera Labs’s careers site →](https://job-boards.greenhouse.io/asteralabs/jobs/4732863005) ## More jobs at Astera Labs ### [Design Verification Tech Lead- SerDes/PHY IP](https://jobs.opennash.com/companies/astera-labs/jobs/1e85866cfa743b0673c9/) San Jose ### [Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms](https://jobs.opennash.com/companies/astera-labs/jobs/5b67cc84296369be4c16/) San Jose ### [Manager, Package Design Engineering](https://jobs.opennash.com/companies/astera-labs/jobs/3878ab9d89d33122f373/) San Jose ### [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://jobs.opennash.com/companies/astera-labs/jobs/6af1a1503a0f9512eca2/) San Jose ### [Principal Analog Mixed-Signal Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/1619cfdca7bbff7012a0/) San Jose ## Similar jobs at other companies ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Senior / Staff Engineer - Digital Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/6af7082b2823e36216a0/) Infineon Technologies · Singapore ### [Digital Design Verification Engineer, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/a645ad2a0d00db966bb8/) Qualcomm · Toronto, Ontario, Canada ### [Digital Design R&D Engineer (Lead/Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/0573bd8ee5eabfcd66a7/) Qualcomm · Bangalore, India ### [Lead Engineer - Digital Design](https://jobs.opennash.com/companies/eaton/jobs/6e5c212cf2b7e641eb70/) Eaton · Hadapsar, Pune, Maharashtra, IND OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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