[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Arista Networks jobs](https://jobs.opennash.com/companies/arista-networks/) · [Search jobs](/search/) Arista Networks · Santa Clara, CA # Senior PCB Design Engineer Santa Clara, CA, United States Full-time Senior individual contributor $133,000 to $180,000 Design Listed on Arista Networks’s official careers site. Posted September 2, 2026. Check that it is still open and apply there. [Apply on Arista Networks’s careers site →](https://jobs.smartrecruiters.com/AristaNetworks/744000147078178-senior-pcb-design-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Arista Networks](https://jobs.opennash.com/companies/arista-networks/) / Senior PCB Design Engineer ## Job description Who You’ll Work With Working closely with cross-functional teams including Hardware Design, Signal Integrity (SI), Power Integrity (PI), Mechanical Engineering, Thermal Engineering, and Manufacturing, our engineers innovate on system architectures and ultra-high-speed PCB designs to deliver state-of- the-art networking platforms. ### What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscale datacenters, and next-generation AI clusters. The team is responsible for end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments — including optical interface platforms up to 800G and 1.6T. ### Core Responsibilities High-Speed Layout & Routing - Implement complex routing for advanced interfaces such as 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6 - Design and route high-speed differential pairs with tight skew and impedance control - Execute dense BGA fan-out for high-pin-count ASICs and FPGAs Optical Transceiver PCB Layout (800G / 1.6T) - Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD or equivalent) Route 112G / 224G PAM4 electrical channels between switch ASICs and optical modules - Define insertion loss budgets and coordinate with SI engineers to meet IEEE compliance requirements - Optimize breakout routing beneath high-density optical cages - Implement via stub mitigation strategies including backdrilling for ultra-high-speed signal paths - Manage ground reference continuity, EMI control, and return path integrity near optical connectors Consider thermal dissipation (20W–30W+ modules) in layout planning ### Impedance Control & Signal Integrity - Design advanced multi-layer stack-ups (20–30+ layers) - Calculate impedance profiles and ensure low-reflection, low-crosstalk performance - Collaborate with SI teams on channel modeling and pre-/post-layout simulations Power Integrity (PI) Optimization - Design robust Power Distribution Networks (PDNs) for high-current ASICs Layout multi-phase DC/DC converters for high transient loads Strategically place decoupling capacitors to ensure wideband impedance stability ### Thermal & Mechanical Coordination - Integrate thermal vias, heat sink attachments, and high-conductivity materials - Coordinate mechanical constraints such as enclosure, airflow, and structural limitations - Ensure proper placement and structural integration of optical cages ### Advanced Fabrication Deliverables - Generate comprehensive manufacturing packages (Gerber, ODB++, IPC-2581) - Define backdrilling parameters and impedance specifications - Ensure compliance with DFM, DFA, and DFT requirements - Support boards through fabrication, assembly, and production ramp ### Library & Feasibility Ownership - Create and maintain high-density component footprints (e.g., large BGAs, optical module connectors) - Participate in new product feasibility studies - Develop detailed routing guidelines and work packages for layout partners - Review external placement and routing work to ensure quality and schedule adherence ## Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field - 10+ years of relevant hardware engineering experience - Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching - Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred) Expertise with 112G / 224G PAM4 routing and channel optimization Advanced proficiency in Cadence Allegro and Sigrity Experience designing 20+ layer boards with 50G+ signals Hands-on experience with sequential lamination, HDI, ultra-low-loss materials Experience in multi-phase DC/DC layout for high-current, high transient loads - Strong manufacturing knowledge including DFM, DFA, and DFT for 30+ layer rigid and rigid-flex boards - Demonstrated success taking products from concept through mass production Compensation Information The new hire base pay for this role has a salary range of $133,000 to $180,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location. #LI-AC1 ## At a glance - Posted by the employer: Sep 2, 2026 - First seen by OpenNash: Oct 10, 2026 - Last checked: Oct 17, 2026 - Listed for: 45 days - Location: Santa Clara, CA, United States - Employment type: Full-time - Pay: $133,000 to $180,000[Apply on Arista Networks’s careers site →](https://jobs.smartrecruiters.com/AristaNetworks/744000147078178-senior-pcb-design-engineer) ## More jobs at Arista Networks ### [FPGA Design Engineer](https://jobs.opennash.com/companies/arista-networks/jobs/76998ba751a7396e5ce7/) Santa Clara, CA, United States ### [Hardware Design Integrity Engineer](https://jobs.opennash.com/companies/arista-networks/jobs/f6230761b445bd2e64d1/) Santa Clara, CA, United States ### [Mechanical Design Engineer (Tooling Design Focus)](https://jobs.opennash.com/companies/arista-networks/jobs/067497ce4258f271bc23/) Santa Clara, CA, United States ### [Senior Hardware Design Engineer, Ethernet Switching](https://jobs.opennash.com/companies/arista-networks/jobs/d12c9787c28cf3cccc49/) Santa Clara, CA, United States ### [BIOS Senior/Lead Software Engineer](https://jobs.opennash.com/companies/arista-networks/jobs/3503762717cbfd4c01cf/) Santa Clara, CA, United States ## Similar jobs at other companies ### [PCB Layout Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/223f969626c59a23169e/) Lockheed Martin · Orlando, FL ### [PCB Design Engineer](https://jobs.opennash.com/companies/general-dynamics/jobs/19c8ca326ab1dcf31bb6/) General Dynamics · Pittsfield, MA, US ### [PCB Design Engineering Section Lead](https://jobs.opennash.com/companies/bae-systems/jobs/338a39d43c07b4b50b25/) BAE Systems · Hudson, New Hampshire, United States ### [Electrical Design Engineer - FPGA & PCB Design](https://jobs.opennash.com/companies/kla/jobs/0afb7ae560a8ab84cb4b/) KLA · Milpitas, CA ### [Staff Digital Design Engineer (PCB Design)](https://jobs.opennash.com/companies/analog-devices/jobs/8dfcc6dc94514c75f7c7/) Analog Devices · US, MA, Chelmsford, Elizabeth OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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