[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Applied Materials jobs](https://jobs.opennash.com/companies/applied-materials/) · [Search jobs](/search/) Applied Materials · Santa Clara, CA # Process Engineer – Die to Wafer Hybrid Bonding Santa Clara, CA Hybrid $147,000.00 - $202,500.00 Manufacturing & Production Listed on Applied Materials’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Applied Materials’s careers site →](https://amat.wd1.myworkdayjobs.com/External/job/Santa-ClaraCA/Process-Engineer---Die-to-Wafer-Hybrid-Bonding--Silicon-Photonics---CPO--R-D-_R2616518) [OpenNash Jobs](https://jobs.opennash.com/) / [Applied Materials](https://jobs.opennash.com/companies/applied-materials/) / Process Engineer – Die to Wafer Hybrid Bonding ## Job description ### Who We Are Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. ### What We Offer Salary: $147,000.00 - $202,500.00 Location: Santa Clara,CA You’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects. Join the Photonics Platforms Business Group at Applied Materials’ Santa Clara headquarters, where you will work with a cross-functional research team to develop cutting-edge 2.5D/3D advanced packaging technologies. We are seeking hands on Process Engineers to drive die to wafer (D2W) hybrid bonding R&D. This role focuses on hybrid bonding process development, pathfinding, technology de risking, and advanced packaging integration exploration. The role provides on the job training and hands on experience with state of the art equipment, including the industry’s first fully integrated die to wafer hybrid bonding system. ### Key Responsibilities - Develop die to wafer hybrid bonding processes, including (but not limited to): Surface preparation and plasma activation High accuracy die placement and alignment Post bond characterization and process evaluation - Integrate D2W bonding with adjacent process modules such as: Dicing and die preparation Die thinning Inter die gap fill and planarization - Design and execute DOE driven experiments to understand process limits, sensitivities, and trade offs. - Own process optimization, perform failure analysis and characterization, and drive continuous engineering improvement. ### Qualifications - Ph.D. or M. S. in Materials Science, Electrical Engineering, Applied Physics, or a related STEM discipline. - In depth knowledge and hands on experience in one or more of the following: Die to wafer or wafer to wafer hybrid bonding Thin die handling and alignment critical processes Micro-LED or CPO experience Heterogeneous integration such as III-V to Si, novel materials to Si 2.5D/3D integration Direct process engineer experience on mainstream semiconductor equipment (plasma, wet clean, overlay/alignment, etc.) - Strong understanding of: Bond interface physics Alignment and overlay fundamentals Mechanical behavior of thin and fragile dies - Proficiency in statistical analysis and process control (e.g., DOE, SPC, JMP). - Self starter with strong problem solving skills; able to work both independently and collaboratively with minimal supervision. - Strong communication and interpersonal skills, with the ability to collaborate effectively across multidisciplinary teams. ### Additional Information Time Type Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 27, 2026 - Last checked: Oct 18, 2026 - Listed for: 83 days - Location: Santa Clara, CA - Work arrangement: Hybrid - Pay: $147,000.00 - $202,500.00[Apply on Applied Materials’s careers site →](https://amat.wd1.myworkdayjobs.com/External/job/Santa-ClaraCA/Process-Engineer---Die-to-Wafer-Hybrid-Bonding--Silicon-Photonics---CPO--R-D-_R2616518) ## More jobs at Applied Materials ### [2027 New College Grad - Process Engineer III - Doctorate (Winter 2026 Start)](https://jobs.opennash.com/companies/applied-materials/jobs/a0fe039b19d794e82da3/) Santa Clara, CA ### [2027 Summer Intern - Process Engineer - BS/MS Degree (Santa Clara, CA)](https://jobs.opennash.com/companies/applied-materials/jobs/33ee7f02a0a695a22c5e/) Santa Clara, CA ### [2027 Summer Intern - Process Engineer - PhD, (Santa Clara)](https://jobs.opennash.com/companies/applied-materials/jobs/dd78fc7cba3486906b70/) Santa Clara, CA ### [Advanced Packaging Process Engineer III (E3)](https://jobs.opennash.com/companies/applied-materials/jobs/642a04c5685bf6eca9fe/) Santa Clara, CA ### [Chemical Delivery/Flow Control Device Quality Engineer E4](https://jobs.opennash.com/companies/applied-materials/jobs/127c1e09ccb4185d57c9/) Santa Clara, CA ## Similar jobs at other companies ### [R&D Process Engineer - Wafer Wet Process Engineer](https://jobs.opennash.com/companies/keysight-technologies/jobs/35139d84b54cbff82c2e/) Keysight Technologies · Santa Rosa, California ### [Wafer Fab Process Engineer](https://jobs.opennash.com/companies/teledyne-technologies/jobs/3ca8b34322440b331adc/) Teledyne Technologies · Goleta, US, CA ### [Staff / Principal Wafer Bond Process Development Engineer](https://jobs.opennash.com/companies/micron-technology/jobs/9fab98a451975631d228/) Micron Technology · Boise, ID - Main Site ### [Sr. Mechanical Design Engineer - Wafer Chucks & Wafer Positioning Stages](https://jobs.opennash.com/companies/kla/jobs/f8c0b1d0c402d0c13e9a/) KLA · Milpitas, CA ### [IC Wafer Fab Process Engineering Technician](https://jobs.opennash.com/companies/keysight-technologies/jobs/f1c2882aac3a8f9068cc/) Keysight Technologies · Santa Rosa, California OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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