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Apple · Herzliya, Israel

# FE STA engineer

Herzliya, Israel Operations 

Listed on Apple’s official careers site. Posted May 28, 2026. Check that it is still open and apply there.
[Apply on Apple’s careers site →](https://jobs.apple.com/en-us/details/200644733/fe-sta-engineer)

[OpenNash Jobs](https://jobs.opennash.com/) / [Apple](https://jobs.opennash.com/companies/apple/) / FE STA engineer

## Job description

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing.

You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

## At a glance
- Posted by the employer: May 28, 2026
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 11, 2026
- Listed for: 136 days
- Location: Herzliya, Israel[Apply on Apple’s careers site →](https://jobs.apple.com/en-us/details/200644733/fe-sta-engineer)

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