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Apple

# CAD Engineer - Timing for Gate-Level Flows & Methodologies

San Jose, United States of America Operations 

Listed on Apple’s official careers site. Posted April 13, 2026. Check that it is still open and apply there.
[Apply on Apple’s careers site →](https://jobs.apple.com/en-us/details/200657612/cad-engineer-timing-for-gate-level-flows-methodologies)

[OpenNash Jobs](https://jobs.opennash.com/) / [Apple](https://jobs.opennash.com/companies/apple/) / CAD Engineer - Timing for Gate-Level Flows & Methodologies

## Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices.

Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon.

## At a glance
- Posted by the employer: Apr 13, 2026
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 188 days
- Location: San Jose, United States of America[Apply on Apple’s careers site →](https://jobs.apple.com/en-us/details/200657612/cad-engineer-timing-for-gate-level-flows-methodologies)

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Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

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