[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Amazon jobs](https://jobs.opennash.com/companies/amazon/) · [Search jobs](/search/) Amazon · Cupertino, CA # SOC Top Level Physical Design Engineer, Annapurna Labs US, CA, Cupertino Design Listed on Amazon’s official careers site. Posted May 11, 2026. Check that it is still open and apply there. [Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs) [OpenNash Jobs](https://jobs.opennash.com/) / [Amazon](https://jobs.opennash.com/companies/amazon/) / SOC Top Level Physical Design Engineer, Annapurna Labs ## Job description Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. ### Key job responsibilities - Drive full chip floorplan, placement, integration, PV signoff and tapeout - Collaborate with FE team to understand RTL and drive physical aspects early in design cycle - Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification - Debug and resolve physical verification issues in collaboration with layout and design teams - Interface with foundries for MT form, rule deck updates and violation waivers; Develop and maintain verification runsets and methodologies - Mentor junior engineers on physical verification methodologies and closure ## At a glance - Posted by the employer: May 11, 2026 - First seen by OpenNash: Oct 18, 2026 - Last checked: Oct 18, 2026 - Listed for: 160 days - Location: US, CA, Cupertino[Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs) ## More jobs at Amazon ### [Automation Process Engineer, Manufacturing Automation Design & Engineering](https://jobs.opennash.com/companies/amazon/jobs/b13199238a5e61de2a2b/) US, CA, Cupertino ### [MLA Design Verification Engineer I, Annapurna Labs](https://jobs.opennash.com/companies/amazon/jobs/1d4cb12ffe7a6ecf094b/) US, CA, Cupertino ### [Physical Design Verification Manager, Annapurna Labs](https://jobs.opennash.com/companies/amazon/jobs/77ac748319b6950bdfdb/) US, CA, Cupertino ### [Power Electronics Engineer, AWS Board Core Design Services, Power Team](https://jobs.opennash.com/companies/amazon/jobs/0a0ea2ff2d10836f8aa1/) US, CA, Cupertino ### [Sr Hardware Development Engineer, AWS Board Core Design and Services Team](https://jobs.opennash.com/companies/amazon/jobs/a035a8a94e51cb29d511/) US, CA, Cupertino ## Similar jobs at other companies ### [Staff SOC Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/2a047bcb54091aea74c4/) Qualcomm · Austin, Texas, United States of America ### [Senior SOC Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/47fffbf12a8acba45831/) Qualcomm · San Diego, California, United States of America ### [SoC Physical Design Engineer, Top Level](https://jobs.opennash.com/companies/apple/jobs/d13bbd04d45910548420/) Apple · Beaverton, United States of America ### [SoC Physical Design Engineer, Top Level](https://jobs.opennash.com/companies/apple/jobs/09e49ea52b745c5e3034/) Apple · Seattle, United States of America ### [Program Manager (NOC/SOC) - TOP SECRET Clearance](https://jobs.opennash.com/companies/ntt/jobs/d345b10a00983a0a2bf3/) NTT · Springfield, VA, US, United States OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)