[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Amazon · Cupertino, CA # ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs US, CA, Cupertino Data & Analytics Listed on Amazon’s official careers site. Posted June 22, 2026. Check that it is still open and apply there. [Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10455432/asic-design-engineer-cloud-scale-machine-learning-acceleration-team-annapurna-labs) [OpenNash Jobs](https://jobs.opennash.com/) / [Amazon](https://jobs.opennash.com/companies/amazon/) / ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs ## Job description Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer, you will: - Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets - Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements - Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints - Execute lint and clock domain crossing quality checks to ensure design integrity - Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts The ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable. ### You will thrive in this role if you - Have a "Learn and Be Curious" mindset - Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures - Have a strong drive to innovate, explore new solutions, and contribute to the company's intellectual property through patents About the team Inclusive Team Culture Here at AWS, we embrace our differences. We are committed to furthering our culture of inclusion. We have ten employee-led affinity groups, reaching 40,000 employees in over 190 chapters globally. We have innovative benefit offerings, and host annual and ongoing learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences. Amazon’s culture of inclusion is reinforced within our 16 Leadership Principles, which remind team members to seek diverse perspectives, learn and be curious, and earn trust. ### Work/Life Balance Our team puts a high value on work-life balance. It isn’t about how many hours you spend at home or at work; it’s about the flow you establish that brings energy to both parts of your life. We believe striking the right balance between your personal and professional life is critical to life-long happiness and fulfillment. We offer flexibility in working hours and encourage you to find your own balance between your work and personal lives. ### Mentorship & Career Growth Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge sharing and mentorship. We care about your career growth and strive to assign projects based on what will help each team member develop into a better-rounded professional and enable them to take on more complex tasks in the future. We are open to hiring candidates to work out of one of the following locations: Cupertino, CA, USA | Austin, TX, USA ## At a glance - Posted by the employer: Jun 22, 2026 - First seen by OpenNash: Oct 25, 2026 - Last checked: Nov 1, 2026 - Listed for: 132 days - Location: US, CA, Cupertino[Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10455432/asic-design-engineer-cloud-scale-machine-learning-acceleration-team-annapurna-labs) ## Hiring at Amazon - Open jobs: 19,174 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Amazon jobs](https://jobs.opennash.com/companies/amazon/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Amazon ### [AI SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS](https://jobs.opennash.com/companies/amazon/jobs/8d3eac5ffb4cfb39dffc/) US, CA, Cupertino ### [ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration](https://jobs.opennash.com/companies/amazon/jobs/2f4abd4b31f6ccf57c50/) US, CA, Cupertino ### [Machine Learning - Compiler Engineer, AWS Neuron, Annapurna Labs](https://jobs.opennash.com/companies/amazon/jobs/113b9c3df6d2ea85d6c4/) US, CA, Cupertino ## Similar jobs at other companies ### [ASIC & FPGA Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/e94b640c48ecc099615e/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [Principal ASIC Design Engineer](https://jobs.opennash.com/companies/fortinet/jobs/9286f067ac1219e2ec7e/) Fortinet · Sunnyvale, CA, United States ### [Digital ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/208c975103db0801757a/) Qualcomm · San Diego, California, United States of America ### [Processor ASIC RTL Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/53e4da287874608df756/) Qualcomm · San Diego, California, United States of America OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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