[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Amazon jobs](https://jobs.opennash.com/companies/amazon/) · [Search jobs](/search/) Amazon · San Diego, CA # ASIC Design Engineer, Satellite Communication US, CA, San Diego Design Listed on Amazon’s official careers site. Posted October 6, 2026. Check that it is still open and apply there. [Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10570952/asic-design-engineer-satellite-communication) [OpenNash Jobs](https://jobs.opennash.com/) / [Amazon](https://jobs.opennash.com/companies/amazon/) / ASIC Design Engineer, Satellite Communication ## Job description Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon! We're hiring a ASIC Digital Design Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP’s. ### The Role Be part of Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a state-of-the-art wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation. - Build complex, high-performance digital solutions and develop solutions by leveraging AI-assisted techniques optimizing customer experience (throughput, latency and availability) while meeting power and cost constraints. - Drive high quality designs for first-time right silicon solutions, and meeting the PPA objectives - Work with the verification team and participate in System level verification using test benches constructed using UVM/System C/DPI-C including test plan development ### Export Control Requirement Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. ### Key job responsibilities · Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. - Define, configure and integrate key IP blocks for SoC - Control plane architecture and implementation for PHY subsystem for the SoC - Configure, instantiate and integrate 3rd party IP blocks - Understand low power design & the impact of DFT on the blocks - Perform initial synthesis & timing analysis - Assist verification team in unit verification including test plan development - Assist with debug and bring-up ## At a glance - Posted by the employer: Oct 6, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 12 days - Location: US, CA, San Diego[Apply on Amazon’s careers site →](https://www.amazon.jobs/en/jobs/10570952/asic-design-engineer-satellite-communication) ## More jobs at Amazon ### [ASIC Design Verification Engineer, Amazon Leo](https://jobs.opennash.com/companies/amazon/jobs/d281fbe5b6515f4c615c/) US, CA, San Diego ### [ASIC Engineer - RF/DSP Systems Design, LEO](https://jobs.opennash.com/companies/amazon/jobs/71daf26c977e20829dbc/) US, CA, San Diego ### [Design Verification Tech Lead Engineer, Amazon Leo](https://jobs.opennash.com/companies/amazon/jobs/0ac513e6d66b8454a33e/) US, CA, San Diego ### [IC Packaging Design Engineer, Amazon Leo](https://jobs.opennash.com/companies/amazon/jobs/826e3cf140690a90f050/) US, CA, San Diego ### [RFIC Design Engineer, Amazon Leo](https://jobs.opennash.com/companies/amazon/jobs/194a723809629a112149/) US, CA, San Diego ## Similar jobs at other companies ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/) Lockheed Martin · Boulder, CO ### [ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/99c4aabaf2f51a99dc1b/) Qualcomm · San Diego, California, United States of America ### [Digital ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/208c975103db0801757a/) Qualcomm · San Diego, California, United States of America ### [Satellite Communication (SATCOM) Engineer - TS/SCI w/Poly](https://jobs.opennash.com/companies/general-dynamics/jobs/d7cdfbaff3913f634fbe/) General Dynamics · McLean, VA, US [Jobs in San Diego, CA](/locations/us/ca/san-diego/)[Jobs in California](/locations/us-ca/)[Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)