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Alphabet · Mountain View, CA

# Silicon Engineer, Power Analysis, DeepMind

Mountain View, CA, USA Operations 

Listed on Alphabet’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there.
[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/143938129714127558-silicon-engineer-power-analysis-deepmind)

[OpenNash Jobs](https://jobs.opennash.com/) / [Alphabet](https://jobs.opennash.com/companies/alphabet/) / Silicon Engineer, Power Analysis, DeepMind

## Job description

### Minimum qualifications

7 years of experience working in ASIC power analysis & optimization, including experience with production chips Experience in tape-outs of chips Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler) Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows Software development experience Preferred qualifications: Master's degree or PhD in Electrical Engineering, Physics or related field About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.

You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 13, 2026
- Last checked: Oct 23, 2026
- Listed for: 10 days
- Location: Mountain View, CA, USA[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/143938129714127558-silicon-engineer-power-analysis-deepmind)

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