[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Alphabet jobs](https://jobs.opennash.com/companies/alphabet/) · [Search jobs](/search/) Alphabet · Sunnyvale, CA # TPU PCIe Design Lead Sunnyvale, CA, USA Manager or lead Design Listed on Alphabet’s official careers site. Listed as of October 13, 2026. Check that it is still open and apply there. [Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/92705565079151302-tpu-pcie-design-lead) [OpenNash Jobs](https://jobs.opennash.com/) / [Alphabet](https://jobs.opennash.com/companies/alphabet/) / TPU PCIe Design Lead ## Job description info_outline About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering AI and machine learning workloads in data centers. As a Peripheral Component Interconnect Express (PCIe) Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. You will build the foundational SoC infrastructure, including clocking, reset, error handling, and chip management that powers silicon beyond designing high-performance PCIe subsystems,. In this highly cross-functional role, you will offer a "big picture" view of the product life-cycle from concept to production, requiring close collaboration with software and hardware teams to deliver accelerators. This position offers the opportunity to work on challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. ### US $192000 - $278000 (USD) + 20% bonus target + equity + benefits Learn more about benefits at Google. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 13, 2026 - Listed for: Under a day - Location: Sunnyvale, CA, USA[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/92705565079151302-tpu-pcie-design-lead) ## More jobs at Alphabet ### [ASIC Design Verification Manager, Google Cloud](https://jobs.opennash.com/companies/alphabet/jobs/2c6e8151497e894ea000/) Sunnyvale, CA, USA ### [ASIC Design Verification Manager, TPU Compute](https://jobs.opennash.com/companies/alphabet/jobs/2269e917243514c253d7/) Sunnyvale, CA, USA ### [Low Power Verification Engineer, Physical Design](https://jobs.opennash.com/companies/alphabet/jobs/4b344d60cc99579cb060/) Sunnyvale, CA, USA ### [Mechanical Product Design Engineer, Platforms](https://jobs.opennash.com/companies/alphabet/jobs/70ab8c21a0a608efac1f/) Sunnyvale, CA, USA ### [Package Design Engineer](https://jobs.opennash.com/companies/alphabet/jobs/b16463b0d0cef9acc625/) Sunnyvale, CA, USA ## Similar jobs at other companies ### [PCIe Design Verification Intern - Summer 2027](https://jobs.opennash.com/companies/nvidia/jobs/721aa73f0183d0672f6a/) NVIDIA · US, TX, Austin ### [PCIe Design Verification Intern - Spring 2027](https://jobs.opennash.com/companies/nvidia/jobs/4033ee61c6c52489d6cf/) NVIDIA · US, CA, Santa Clara ### [System Development Eng, PCIe, AWS PCIe and Signal Integrity Team](https://jobs.opennash.com/companies/amazon/jobs/5fb7f1a2c4a0725750a4/) Amazon · US, WA, Seattle ### [Sr. Staff/Principal PCIE Subsystem Architect](https://jobs.opennash.com/companies/qualcomm/jobs/b14af4b20c7c51b9fa62/) Qualcomm · Santa Clara, California, United States of America, Austin, Texas, San Diego ### [ARM Server Platform I/O & Interconnect Software Architect (PCIe, CXL & Interrupt Architecture)](https://jobs.opennash.com/companies/qualcomm/jobs/0e7ef4d89bfd52b09a19/) Qualcomm · Santa Clara, California, United States of America, Austin, Texas, Folsom, Hillsboro, Oregon, San Diego OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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