[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Alphabet · Sunnyvale, CA # Senior ASIC Physical Design Engineer Sunnyvale, CA, USA Senior individual contributor Design Listed on Alphabet’s official careers site. Listed as of October 30, 2026. Check that it is still open and apply there. [Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/102063824223249094-senior-asic-physical-design-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Alphabet](https://jobs.opennash.com/companies/alphabet/) / Senior ASIC Physical Design Engineer ## Job description info_outline About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. ### US $163000 - $236000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 23, 2026 - Last checked: Oct 30, 2026 - Listed for: 7 days - Location: Sunnyvale, CA, USA[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/102063824223249094-senior-asic-physical-design-engineer) ## Hiring at Alphabet - Open jobs: 3,591 - New in the last 7 days: After two weekly collections - Tracked since: Aug 20, 2026 [All Alphabet jobs](https://jobs.opennash.com/companies/alphabet/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Alphabet ### [ASIC Design Verification Manager, Google Cloud](https://jobs.opennash.com/companies/alphabet/jobs/27f42ee07299fede983e/) Sunnyvale, CA, USA ### [ASIC Design Verification Manager, TPU Compute](https://jobs.opennash.com/companies/alphabet/jobs/2269e917243514c253d7/) Sunnyvale, CA, USA ### [Design Verification Engineer, Google Cloud TPU](https://jobs.opennash.com/companies/alphabet/jobs/f6ce60859dad6ccfecdb/) Sunnyvale, CA, USA ### [Electrical Design Engineer, Platforms](https://jobs.opennash.com/companies/alphabet/jobs/fd833f3c0c0554e10028/) Sunnyvale, CA, USA ### [Low Power Verification Engineer, Physical Design](https://jobs.opennash.com/companies/alphabet/jobs/4b344d60cc99579cb060/) Sunnyvale, CA, USA ## Similar jobs at other companies ### [ASIC & FPGA Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/e94b640c48ecc099615e/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [Principal ASIC Design Engineer](https://jobs.opennash.com/companies/fortinet/jobs/9286f067ac1219e2ec7e/) Fortinet · Sunnyvale, CA, United States ### [Digital ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/208c975103db0801757a/) Qualcomm · San Diego, California, United States of America ### [Processor ASIC RTL Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/53e4da287874608df756/) Qualcomm · San Diego, California, United States of America OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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