[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Alphabet jobs](https://jobs.opennash.com/companies/alphabet/) · [Search jobs](/search/)

Alphabet · Sunnyvale, CA

# Senior ASIC Design Verification Engineer, Cloud

Sunnyvale, CA, USA Senior individual contributor Design 

Listed on Alphabet’s official careers site. Listed as of October 13, 2026. Check that it is still open and apply there.
[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/132879480132641478-senior-asic-design-verification-engineer-cloud)

[OpenNash Jobs](https://jobs.opennash.com/) / [Alphabet](https://jobs.opennash.com/companies/alphabet/) / Senior ASIC Design Verification Engineer, Cloud

## Job description

info_outline About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. The AI and Infrastructure team is redefining what’s possible.

We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.

From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

### US

$163000 - $236000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 13, 2026
- Last checked: Oct 13, 2026
- Listed for: Under a day
- Location: Sunnyvale, CA, USA[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/132879480132641478-senior-asic-design-verification-engineer-cloud)

## More jobs at Alphabet

### [ASIC Design Verification Manager, Google Cloud](https://jobs.opennash.com/companies/alphabet/jobs/2c6e8151497e894ea000/)

Sunnyvale, CA, USA

### [ASIC Design Verification Manager, TPU Compute](https://jobs.opennash.com/companies/alphabet/jobs/2269e917243514c253d7/)

Sunnyvale, CA, USA

### [Low Power Verification Engineer, Physical Design](https://jobs.opennash.com/companies/alphabet/jobs/4b344d60cc99579cb060/)

Sunnyvale, CA, USA

### [Mechanical Product Design Engineer, Platforms](https://jobs.opennash.com/companies/alphabet/jobs/70ab8c21a0a608efac1f/)

Sunnyvale, CA, USA

### [Package Design Engineer](https://jobs.opennash.com/companies/alphabet/jobs/b16463b0d0cef9acc625/)

Sunnyvale, CA, USA

## Similar jobs at other companies

### [ASIC Design Verification Engineer (Santa Clara, CA)](https://jobs.opennash.com/companies/qualcomm/jobs/ff2a97a9facc09977ec8/)

Qualcomm · Santa Clara, California, United States of America

### [ASIC & FPGA Verification Engineer Stf - E4](https://jobs.opennash.com/companies/lockheed-martin/jobs/58c48e168348ca7316aa/)

Lockheed Martin · Denver, CO, Sunnyvale, CA

### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/)

Lockheed Martin · Liverpool, NY

### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/)

Qualcomm · Tijuana, Baja California, Mexico

### [ASIC Design Verification Engineer, Amazon Leo](https://jobs.opennash.com/companies/amazon/jobs/3fb192b4b62ec2921de0/)

Amazon · US, TX, Austin

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)
