[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Alphabet jobs](https://jobs.opennash.com/companies/alphabet/) · [Search jobs](/search/) Alphabet · Sunnyvale, CA # Physical Design Engineer, 3D Technology Sunnyvale, CA, USA Design Listed on Alphabet’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there. [Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/107699429053473478-physical-design-engineer-3d-technology) [OpenNash Jobs](https://jobs.opennash.com/) / [Alphabet](https://jobs.opennash.com/companies/alphabet/) / Physical Design Engineer, 3D Technology ## Job description info_outline About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer, 3D Technology you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore’s Law while delivering cutting edge ASIC’s and SoC’s. You will help develop new 3D technology physical design methodologies to drive best product PPA by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs. You will drive new physical design flows that co-optimize across the entire design methodology space–including 3D–and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with Through-Silicon Vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. ### US $138000 - $197000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 23, 2026 - Listed for: 10 days - Location: Sunnyvale, CA, USA[Apply on Alphabet’s careers site →](https://www.google.com/about/careers/applications/jobs/results/107699429053473478-physical-design-engineer-3d-technology) ## More jobs at Alphabet ### [ASIC Design Verification Manager, Google Cloud](https://jobs.opennash.com/companies/alphabet/jobs/27f42ee07299fede983e/) Sunnyvale, CA, USA ### [ASIC Design Verification Manager, TPU Compute](https://jobs.opennash.com/companies/alphabet/jobs/2269e917243514c253d7/) Sunnyvale, CA, USA ### [Electrical Design Engineer, Platforms](https://jobs.opennash.com/companies/alphabet/jobs/fd833f3c0c0554e10028/) Sunnyvale, CA, USA ### [Low Power Verification Engineer, Physical Design](https://jobs.opennash.com/companies/alphabet/jobs/4b344d60cc99579cb060/) Sunnyvale, CA, USA ### [Mechanical Product Design Engineer, Platforms](https://jobs.opennash.com/companies/alphabet/jobs/70ab8c21a0a608efac1f/) Sunnyvale, CA, USA ## Similar jobs at other companies ### [Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/dda9e8d7a67c5354a6eb/) Qualcomm · Tijuana, Baja California, Mexico ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/831567c9a5b68f024d18/) Qualcomm · Austin, Texas, United States of America ### [Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/c6f51a8f2a250a28e52f/) Microsoft · United States, Oregon, Hillsboro, California, Mountain View, North Carolina, Raleigh ### [Physical Design Engineer II (IC)](https://jobs.opennash.com/companies/arrow-electronics/jobs/ec91eccc72f42a5fcfc2/) Arrow Electronics · San Jose, CA, United States of America ### [Senior Physical Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/e7e19400d6681015759d/) Microsoft · United States, Oregon, Hillsboro, California, Mountain View, Texas, Austin, North Carolina, Raleigh, Washington, Redmond OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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