[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Advanced Micro Devices (AMD) jobs](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) · [Search jobs](/search/) Advanced Micro Devices (AMD) · Santa Clara, California # Power Methodology and Modelling Engineer Santa Clara, California Full-time Operations Listed on Advanced Micro Devices (AMD)’s official careers site. Posted October 7, 2026. Check that it is still open and apply there. [Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/93170/login) [OpenNash Jobs](https://jobs.opennash.com/) / [Advanced Micro Devices (AMD)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) / Power Methodology and Modelling Engineer ## Job description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE The focus of this role is to drive SoC power efficiency methodology with a primary focus on RTL and architecture. The engineer will support the development of IP and SoC power models, analyze power-performance tradeoffs, and identify opportunities to improve power efficiency across AMD products. THE PERSON You have a passion for modern processor architecture, digital design, and verification. You are a collaborative team player with strong communication skills and experience working across global teams and time zones. You possess excellent analytical and problem-solving abilities, a passion for learning, and the initiative to tackle complex technical challenges. ### KEY RESPONSIBILITIES Contribute to SoC power methodology, RTL power analysis, and optimization to improve power efficiency across the SoC. Collaborate with architecture, RTL design, verification, and power teams to identify, evaluate, and implement power-efficiency features and enhancements. Analyze power and performance tradeoffs using power models, RTL simulations, workloads, and design data to support product power targets. Evaluate simulation and emulation traces for power projection and correlate projections with power-model predictions and silicon data when available. Support the development and continuous improvement of SoC power models and methodologies, with opportunities to grow ownership of power-modeling activities. Analyze power results, identify key power contributors and anomalies, and work with design teams to drive RTL power optimizations. Drive power-efficiency ideas from concept through RTL implementation, validation, and measurable power improvements. Apply power methodology and analysis techniques to identify and implement RTL and SoC-level power-efficiency enhancements. ### PREFERRED EXPERIENCE Strong foundation in RTL design, digital logic, and SoC architecture, with exposure to CPU, memory subsystems, fabrics, I/O, clocking, or power-management features. Experience with, or strong interest in, RTL power analysis, low-power design techniques, power methodology, and power-efficiency optimization. Understanding of power-management concepts and how architecture and RTL design decisions impact SoC power and performance. Exposure to power modeling, power projection, and model-based power analysis methodologies. Experience with hardware emulation and the use of emulation traces for power projection and analysis is a plus. Interest in learning and growing expertise in SoC power modeling, methodology development, power projection, validation, and correlation. Strong analytical and problem-solving skills with the ability to identify and drive power-efficiency opportunities across engineering disciplines. Programming and scripting experience, with Python preferred. ACADEMIC CREDENTIALS Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. LOCATION Santa Clara, CA #LI-PA1 This role is not eligible for visa sponsorship. ### Benefits offered are described AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. ## At a glance - Posted by the employer: Oct 7, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 11 days - Location: Santa Clara, California - Employment type: Full-time[Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/93170/login) ## More jobs at Advanced Micro Devices (AMD) ### [2027 Masters Thermal Engineering Intern/Co-Op](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/050c29ac21ccca94a142/) Santa Clara, California ### [2027 Undergrad Thermal Engineering Intern/Co-Op](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/cbf01e70bfe70f61b749/) Santa Clara, California ### [AI / ML DFT Project Lead](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/e104620ed93c3285f69a/) Santa Clara, California ### [AI Engineer, Recursive Self-Improvement for Compute](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/5e4db79f33ed709027ae/) Santa Clara, California ### [ASIC Emulation Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/b39ed9509792936b6d6e/) Santa Clara, California ## Similar jobs at other companies ### [ASIC Timing and Methodology Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/9a3a66e840e1ae3025fb/) Qualcomm · Tijuana, Baja California, Mexico ### [Emulation Performance Methodology & Debug Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/571d0163a463c21368ea/) Qualcomm · Tijuana, Baja California, Mexico ### [Senior Engineer Digital Verification and Methodology](https://jobs.opennash.com/companies/infineon-technologies/jobs/2d16b46260c7b36e8f08/) Infineon Technologies · Lexington, KY ### [Staff Engineer Digital Verification and Methodology](https://jobs.opennash.com/companies/infineon-technologies/jobs/d9074188ee6fe932ddd6/) Infineon Technologies · Lexington, KY ### [Senior DFT Power Methodology Engineer](https://jobs.opennash.com/companies/nvidia/jobs/2f1ef76bd8351745880b/) NVIDIA · US, CA, Santa Clara OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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