[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Advanced Micro Devices (AMD) jobs](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) · [Search jobs](/search/) Advanced Micro Devices (AMD) · San Jose, California # SerDes RTL Design Engineer San Jose, California Full-time Design Listed on Advanced Micro Devices (AMD)’s official careers site. Posted September 12, 2026. Check that it is still open and apply there. [Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/91913/login) [OpenNash Jobs](https://jobs.opennash.com/) / [Advanced Micro Devices (AMD)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) / SerDes RTL Design Engineer ## Job description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. ### THE ROLE AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. ### THE PERSON You have an innovative mindset and a passion for digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. ### KEY RESPONSIBILITIES - Collaborate with system link architects to micro-architect cutting edge high-speed SerDes PHY design RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing, clock-data-recovery - Apply low power design techniques and perform PPA analysis - Verify intended functionality with block-level test bench - Run design checker tools such as LINT/CDC/RDC etc. Behavioral modeling of custom circuit using Verilog/System Verilog - Support functional verification and debug of design, and static timing closure - Collaborate with physical design and validation teams to perform pre-tape out design sign-off and silicon bring-up PREFERRED EXPERIENCE: Proficient in logic design concepts and RTL coding using Verilog/System Verilog - Proficient in micro-architecture and developing design specifications - Proficient with design checker tools and/or functional verification tools - Knowledge of synthesis flow and static timing analysis - Knowledge of low power design and methodology Experience in design with multiple clock domains Experience in mixed signal design Experience with Python, Perl, TCL and/or other scripting language Experience with SerDes PHY (PMA/PCS) and/or high-speed I/O protocol is preferred ACADEMIC CREDENTIALS: Bachelor's or master’s degree in electrical engineering, computer engineering, or related field LOCATION: San Jose, CA or anywhere in the US This role is not eligible for visa sponsorship. #LI-MO2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. ## At a glance - Posted by the employer: Sep 12, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 36 days - Location: San Jose, California - Employment type: Full-time[Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/91913/login) ## More jobs at Advanced Micro Devices (AMD) ### [AI Design Automation Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/4d8930bdfb6ea34d4c93/) San Jose, California ### [ASIC Design STA Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/59932d142c44a7949065/) San Jose, California ### [Analog/Mixed-Signal SerDes Design Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/6f209be4bd0243cf7fc1/) San Jose, California ### [Director FPGA Silicon Design Engineering](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/47dd21b1b2508bd5e84c/) San Jose, California ### [Electrical Packaging Design Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/6b059be906d6065be102/) San Jose, California ## Similar jobs at other companies ### [Processor ASIC RTL Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/53e4da287874608df756/) Qualcomm · San Diego, California, United States of America ### [ASIC/RTL Design Engineer for High-speed Interfaces](https://jobs.opennash.com/companies/qualcomm/jobs/c7c4165f56c898fdbb22/) Qualcomm · San Diego, California, United States of America ### [Mixed Signal RTL Design Engineer](https://jobs.opennash.com/companies/apple/jobs/daec80e3e4af3d4dd7bc/) Apple · Cupertino, United States of America ### [Mixed Signal RTL Design Engineer](https://jobs.opennash.com/companies/apple/jobs/c5109aba1919affff4ec/) Apple · Sunnyvale, United States of America ### [Senior SerDes & Analog Layout Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/2e4faa4fba390e5703a2/) Microsoft · United States, North Carolina, Raleigh, Texas, Austin, District of Columbia, Washington D.C., Washington, Redmond, Idaho, Boise, Oregon, Hillsboro, California, Mountain View [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)