[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Advanced Micro Devices (AMD) · Hyderabad, India # Lead FPGA Timing & Characterization Silicon Design Engineer Hyderabad, India Full-time Manager or lead Design Listed on Advanced Micro Devices (AMD)’s official careers site. Posted October 27, 2026. Check that it is still open and apply there. [Apply on Advanced Micro Devices (AMD)’s careers site →](https://global-external-amd.icims.com/jobs/93811/login) [OpenNash Jobs](https://jobs.opennash.com/) / [Advanced Micro Devices (AMD)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) / Lead FPGA Timing & Characterization Silicon Design Engineer ## Job description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Lead FPGA Timing & Characterization Silicon Design Engineer We are seeking a highly motivated and experienced Senior Member of Technical Staff (SMTS) to lead the development, validation, silicon correlation, and release of FPGA timing models. The successful candidate will drive timing characterization methodologies, improve timing model quality and accuracy, collaborate across architecture, silicon design, STA, software, and validation teams, and ensure timely delivery of production-quality timing models that enable industry-leading FPGA implementation and timing analysis tools. Roles and Responsibilities Establish comprehensive validation frameworks for FPGA timing library quality assessment. Drive root-cause analysis for timing discrepancies and model inaccuracies. Develop and maintain regression suites, DRC checks, and release signoff criteria. Drive characterization of FPGA resources Develop automation flows to improve FPGA timing quality Own planning and execution of Timing Library releases aligned with software release schedules. Perform QoR analysis on Vivado software and compare timing results across releases, speed grades, and device generations. Coordinate release readiness reviews and manage risk mitigation plans. Provide technical status updates to engineering leadership and product stakeholders. ### Required Qualifications MTech or MS in Electronics Engineering. 10+ years of experience in FPGA design development & implementation, timing analysis, Silicon characterization Strong understanding of: FPGA architecture and timing closure Static Timing Analysis (STA), PVT variation and timing margins, OCV/POCV methodologies Experience with silicon characterization and model generation flows. Proficiency in scripting and automation using Python, Perl, Tcl, or similar languages. Strong debugging and root-cause analysis skills. Familiarity with large-scale flow automation and data analytics. Experience with Vivado or Quartus FPGA tools Knowledge of silicon correlation and statistical timing techniques. Experience leading cross-functional technical initiatives. ### Expectations Serve as the technical authority for FPGA timing library methodologies and releases. Drive improvements in prediction accuracy, release quality, and characterization productivity. Influence roadmaps, timing methodologies, and next-generation FPGA timing modeling strategies. Mentor engineers and establish engineering best practices across the organization. Lead technically challenging projects with significant product and customer impact. Success Metrics On-time delivery of timing library releases. Silicon correlation accuracy improvement. Reduction in customer timing escapes. Improved QoR consistency across releases. Increased automation and productivity of characterization flows. Successful execution of strategic timing-modeling initiatives. #LI-SG2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. ## At a glance - Posted by the employer: Oct 27, 2026 - First seen by OpenNash: Nov 1, 2026 - Last checked: Nov 1, 2026 - Listed for: 5 days - Location: Hyderabad, India - Employment type: Full-time[Apply on Advanced Micro Devices (AMD)’s careers site →](https://global-external-amd.icims.com/jobs/93811/login) ## Hiring at Advanced Micro Devices (AMD) - Open jobs: 1,273 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Advanced Micro Devices (AMD) jobs](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Advanced Micro Devices (AMD) ### [ASIC Design Verification Lead](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/ae0fba86a9f93c234ec7/) Hyderabad, India ### [ASIC Physical design Lead](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/ea5bd1a08d6d583ac50c/) Hyderabad, India ### [DFX Design - Arch](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/913b1e96fee577f5f3e8/) Hyderabad, India ### [FPGA/RTL Design Engineering Manager with High-Speed Protocols (HSIO) (PCIE/Ethernet/USB)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/293a14496773d83a262b/) Hyderabad, India ### [Lead CPU Design Verification Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/7215160d50df096aa379/) Hyderabad, India ## Similar jobs at other companies ### [Staff Application Engineer – ECO Timing](https://jobs.opennash.com/companies/synopsys/jobs/761c59b76f3715e8d576/) Synopsys · Hyderabad, India ### [Timing & Power Characterization Engineer](https://jobs.opennash.com/companies/capgemini/jobs/5c35a85fde713bd8b8a7/) Capgemini · Brasov, Bucharest, Bucuresti, Cluj-Napoca, Iasi, BUCHARESTSEIMAFOF, BUH, RO, Timisoara ### [Silicon Validation/Characterization Engineer - 18757](https://jobs.opennash.com/companies/synopsys/jobs/d570d73a4accdf348e4a/) Synopsys · Nepean, Canada ### [Silicon Characterization Engineer (m/f/d)](https://jobs.opennash.com/companies/apple/jobs/a5e138525c71ce0a9122/) Apple · Livorno, Italy ### [Software Engineering Technical Leader – Silicon One Software (Timing & Synchronization)](https://jobs.opennash.com/companies/cisco-systems/jobs/95ee9cab18f46e3b6de6/) Cisco Systems · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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