[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Advanced Micro Devices (AMD) jobs](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) · [Search jobs](/search/) Advanced Micro Devices (AMD) · MARKHAM, Canada # Physical Design Engineer MARKHAM, Canada Full-time Design Listed on Advanced Micro Devices (AMD)’s official careers site. Posted September 23, 2026. Check that it is still open and apply there. [Apply on Advanced Micro Devices (AMD)’s careers site →](https://canadacareers-amd.icims.com/jobs/92548/login) [OpenNash Jobs](https://jobs.opennash.com/) / [Advanced Micro Devices (AMD)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) / Physical Design Engineer ## Job description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE AMD is seeking an experienced Tile Place & Route (PnR) Lead to lead the physical implementation and execution of complex SoC designs at advanced process nodes. This role combines deep technical expertise in physical design with leadership responsibilities across multiple programs, engineers, and cross-functional teams. As a Tile PnR Lead, you will be responsible for driving implementation strategy, execution planning, design quality, schedule adherence, and technical mentorship. You will work closely with Architecture, RTL Design, Timing, CAD, Methodology, Physical Verification, and Full Chip teams to deliver world-class products. THE PERSON The ideal candidate is a recognized technical leader with a proven track record of delivering high-quality silicon across multiple successful tape-outs. You are equally comfortable solving challenging technical problems, mentoring engineers, driving execution across global teams, and influencing methodology direction. You possess strong communication skills and can effectively engage customers, project leadership, methodology teams, and senior management while maintaining focus on execution excellence. ### KEY RESPONSIBILITIES Technical Leadership Lead physical implementation of complex SoC tiles from floorplan through tapeout. Drive overall Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness. Define implementation methodologies and best practices to improve PPA, scalability, and design quality. Drive technical decisions impacting schedule, product quality, and silicon success. Lead root-cause analysis and resolution of complex implementation challenges. Program Execution Own execution planning, milestones, risk management, and quality metrics for critical IPs and SoC tiles. Coordinate activities across Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams. Drive closure on schedule-critical and tapeout-critical issues. Provide regular status updates to technical and management leadership. Team Leadership & Mentorship Mentor and develop Tile PnR engineers across multiple experience levels. Conduct technical reviews and provide implementation guidance. Lead training and knowledge-sharing initiatives across the organization. Innovation Drive adoption of new implementation methodologies, automation, and AI-enabled design solutions. Influence future physical design flows and tool direction. Partner with CAD teams to improve productivity, scalability, and design predictability. ### PREFERRED QUALIFICATIONS BS/MS in Electrical Engineering, Computer Engineering, or related field. Industry experience in physical design. Demonstrated technical leadership across multiple projects or product families. Multiple successful tape-outs at advanced technology nodes. Proven experience leading critical tiles or IPs. Recognized expert in Tile PnR and physical implementation. Experience leading globally distributed engineering teams. Expertise in congestion analysis, timing architecture, power optimization, and PPA improvement. Experience with AI-assisted implementation methodologies. Familiarity with ICC2, Innovous, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows. Working knowledge of IREM is considered a strong plus. Location Markham, ON #LI-JE1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. ## At a glance - Posted by the employer: Sep 23, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 25 days - Location: MARKHAM, Canada - Employment type: Full-time[Apply on Advanced Micro Devices (AMD)’s careers site →](https://canadacareers-amd.icims.com/jobs/92548/login) ## More jobs at Advanced Micro Devices (AMD) ### [AI Platform Engineer, Silicon Design Infrastructure](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/84198997e09570eef60e/) MARKHAM, Canada ### [Analog Designer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/8a047c66f693a0e54c50/) MARKHAM, Canada ### [Analog/Mixed-Signal SerDes Design Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/3e591e287e5ed394dd4c/) MARKHAM, Canada ### [DFT Design Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/2b8c99edef67fdc73d32/) MARKHAM, Canada ### [Design Verification Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/e2be4ea731b7a2a00a65/) MARKHAM, Canada ## Similar jobs at other companies ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/27bd54e804c3da2d6519/) Qualcomm · Bangalore, India ### [NPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/916f75702172388c2ee7/) Qualcomm · Bangalore, India ### [Physical Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/2d7f9c2e826bc117df12/) Microsoft · India, Karnataka, Bangalore ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [Senior Staff Engineer Physical Design and Methodology (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/46bbe226ff31021fb81f/) Infineon Technologies · Munich [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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