[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Advanced Micro Devices (AMD) · San Jose, California # Silicon Diagnosis DFT Engineer San Jose, California Full-time Operations Listed on Advanced Micro Devices (AMD)’s official careers site. Posted October 22, 2026. Check that it is still open and apply there. [Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/93718/login) [OpenNash Jobs](https://jobs.opennash.com/) / [Advanced Micro Devices (AMD)](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) / Silicon Diagnosis DFT Engineer ## Job description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. ### THE ROLE Looking for a diagnose expert, with scan DFT knowledge, to improve/enhance debug and diagnosis capabilities and implement features to meet new diagnosis challenges. In the role of a PMTS, you will conduct electrical/physical fault isolation by generating diagnosis patterns and collaborating with design, verification, test engineering, and yield analysis groups. ### THE PERSON Proficient in IC design/automation, silicon product validation, characterization, or debug/diagnosis, in particular using scan DFT techniques. Experiences of using commercial tools for ATPG and pattern validations. Have st rong problem solving, communication, and teamwork skills. Motivated and proactive, willing to adapt and learn new techniques. ### KEY RESPONSIBILITIES Perform post-silicon electrical/physical fault isolation. Work with verification and test team to make diagnosable tests. Build layout databases for diagnosis and cross-probing. Generate scan diagnosis tests for fault isolation. Automate volume diagnosis and data analysis. Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging. Work with design and DFX team for diagnosable designs. ### PREFERRED EXPERIENCE Familiar with C/C++ or Verilog Fluent in scripting (Perl/Python/TCL) Experience in IC process technology, ATE, yield analysis or memory design, layout design, FPGA design tools (Xilinx Vivado) or any validation tools (VCS, Caliber, Primetime). ### ACADEMIC CREDENTIALS Degrees in Electrical Engineering, with knowledge of IC design/verification/DFT (RTL, circuit, physical), and semiconductor physics. ### LOCATION San Jose, CA This role is not eligible for visa sponsorship. #LI-AJ1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. ## At a glance - Posted by the employer: Oct 22, 2026 - First seen by OpenNash: Oct 25, 2026 - Last checked: Nov 1, 2026 - Listed for: 10 days - Location: San Jose, California - Employment type: Full-time[Apply on Advanced Micro Devices (AMD)’s careers site →](https://careers-amd.icims.com/jobs/93718/login) ## Hiring at Advanced Micro Devices (AMD) - Open jobs: 1,273 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Advanced Micro Devices (AMD) jobs](https://jobs.opennash.com/companies/advanced-micro-devices-amd/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Advanced Micro Devices (AMD) ### [AI Solution Architect](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/663e3d5f07f50ae6f756/) San Jose, California ### [AI/ML Silicon Verification Solutions Engineer – Tools](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/9bf6e834066252c74fe4/) San Jose, California ### [Advanced AI Workloads - Performance and Scalability Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/4ad83f473054074d36ed/) San Jose, California ### [DFT Architect](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/75a9f020105391d3362d/) San Jose, California ### [Embedded Systems Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/b23a2c9b36e233327fc6/) San Jose, California ## Similar jobs at other companies ### [Senior DFT - Silicon Validation Engineer](https://jobs.opennash.com/companies/nvidia/jobs/05b169720f0b76e7a042/) NVIDIA · US, CA, Santa Clara ### [DFT Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/d12bdf13ea3fe1f9d9a4/) Qualcomm · Tijuana, Baja California, Mexico ### [DFT Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/28e4aaa038c98a1c41c2/) Qualcomm · San Diego, California, United States of America ### [Senior FPGA/Silicon Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/64971b5dd3f0b00b95e0/) Microsoft · United States, Washington, Redmond, California, Mountain View ### [ASIC Post silicon DFT Technical Leader](https://jobs.opennash.com/companies/cisco-systems/jobs/9044b2ca3c3f286a3af5/) Cisco Systems · Austin, Texas, United States of America +1 more OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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